1. Field of the Invention
This invention relates to semiconductor device fabrication and more particularly to a method and structure for reducing capacitive coupling by first forming a multilevel interconnect structure and then dissolving or otherwise removing the interlevel material so that the interlevel dielectric comprises air.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a "bus". A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memory and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses, and control busses.
Conductors within a bus generally extend parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. The topography can also include one or more layers of conductors which are sealed by an upper layer of dielectric material. Accordingly, the layers of conductors overlaid with a dielectric present a topography upon which a subsequent layer of conductors can be patterned.
Conductors are made from an electrically conductive material, a suitable material includes Cu, Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate is a silicon-based material which receives p-type and/or n-type ions. Active devices are contacted by the conductors to form an integrated circuit.
Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and spaced above an underlying conductor or substrate by a dielectric of thickness T.sub.d1. Each conductor is dielectrically spaced from other conductors within the same level of conductors by a distance T.sub.d2. Accordingly, interlevel capacitance C.sub.LS (i.e., capacitance between conductors on different levels) is determined as follows: EQU C.sub.LS .apprxeq..epsilon.W.sub.L L/T.sub.d1 (Eq. 1)
Further, the intralevel capacitance C.sub.LL (i.e., capacitance between conductors on the same level) is determined as follows: EQU C.sub.LL .apprxeq..epsilon.T.sub.c L/T.sub.d2 (Eq. 2)
where .epsilon. is the permittivity of the dielectric material, W.sub.L is the conductor width, T.sub.c is the conductor thickness, and L is the conductor length. The resistance R of the conductor is calculated as follows: EQU R=(.rho.L)/W.sub.L T.sub.c (Eq. 3)
where .rho. represents resistivity of the conductive material, and T.sub.c is the interconnect thickness. Combinations of equations 1 and 3, and/or equations 2 and 3 indicate the propagation delay of a conductor as follows: EQU RC.sub.LS .apprxeq..rho..epsilon.L.sup.2 /T.sub.c T.sub.d1 EQU RC.sub.LL .apprxeq..rho..epsilon.L.sup.2 /W.sub.L T.sub.d2 (Eq. 4)
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay be minimized as much as possible within the geometric constraints of the semiconductor topography.
Equation 4 shows that the propagation delay of a circuit is determined by parasitic capacitance values (C.sub.LL) between laterally spaced conductors, and parasitic capacitance values (C.sub.LS) between vertically spaced conductors or between a conductor and the underlying substrate. As circuit density increases, lateral spacing and vertical spacing between conductors decrease and capacitance C.sub.LL increases. Meanwhile, planarization mandates to some extent a decrease in vertical spacing. Shallow trench processing, recessed LOCOS processing, and multi-layered interlevel dielectrics can bring about an overall reduction in vertical spacing and therefore an increase in C.sub.LS. Depending upon the geometries associated with a particular device, either C.sub.LL or C.sub.LS can reduce the performance of the device. Integrated circuits which employ narrow interconnect spacings thereby define C.sub.LL as a predominant capacitance, and integrated circuits which employ thin interlevel dielectrics define C.sub.LS as a predominant capacitance.
It is therefore important to minimize propagation delay especially in critical speed paths. Given the constraints of chemical compositions, it is not readily plausible to reduce the resistivity .rho. of conductor materials. Geometric constraints make it difficult to increase conductor thickness T.sub.c or dielectric thickness T.sub.d1 or T.sub.d2. Still further, instead of reducing length L of a conductor, most modern integrated circuits employ long interconnect lines which compound the propagation delay problems. Accordingly, a need arises for instituting a reduction in propagation delay within the chemical and geometric constraints of existing fabrication processes. It is therefore desirable that a fabrication process be derived that employs a low permittivity dielectric material.
The permittivity of any given material is commonly expressed as a product of the permittivity constant (.epsilon..sub.0 =8.854.times.10.sup.-14) and the dielectric constant (K) of the material. Dielectric constants for various materials are shown in Table A.
TABLE A ______________________________________ Material Dielectric Constant ______________________________________ Titanium dioxide 100 Water 78 Silicon 11.8 Silicon Nitride 6-9 CVD Oxide 3.8-4.5 Thermal Silicon Dioxide 3.8-4.0 Air 1.00054 Vacuum 1.00000 ______________________________________
Table A reveals that the materials commonly encountered in semiconductor manufacturing have dielectric constants at least three times greater than the dielectric constant of air. Processing techniques that incorporate air gaps into an interlevel dielectric material such as silicon dioxide achieve some reduction in the overall permittivity of the dielectric structure but fall far short of the reduction in capacitive coupling that could be achieved if the interlevel dielectric was entirely comprised of air. It would therefore be desirable to fabricate a multilevel interconnect structure in which the interlevel dielectric is air. Achieving such a structure requires consideration of how to provide adequate physical support for each interconnect level and how to protect each interconnect level from physical damage and moisture. These goals must be achieved without adding undue complexity or expense to the manufacturing process.